kernel/uart.c
161 lines
1//2// low-level driver for 16550a UART.3//45#include "types.h"6#include "param.h"7#include "memlayout.h"8#include "riscv.h"9#include "spinlock.h"10#include "proc.h"11#include "defs.h"1213// the UART control registers are memory-mapped14// at address UART0. this macro returns the15// address of one of the registers.16#define Reg(reg) ((volatile unsigned char *)(UART0 + (reg)))1718#define ReadReg(reg) (*(Reg(reg)))19#define WriteReg(reg, v) (*(Reg(reg)) = (v))2021// the UART control registers.22// some have different meanings for read vs write.23// see http://byterunner.com/16550.html24#define RHR 0 // receive holding register (for input bytes)25#define THR 0 // transmit holding register (for output bytes)26#define IER 1 // interrupt enable register27#define IER_RX_ENABLE (1<<0)28#define IER_TX_ENABLE (1<<1)29#define FCR 2 // FIFO control register30#define FCR_FIFO_ENABLE (1<<0)31#define FCR_FIFO_CLEAR (3<<1) // clear the content of the two FIFOs32#define ISR 2 // interrupt status register33#define LCR 3 // line control register34#define LCR_EIGHT_BITS (3<<0)35#define LCR_BAUD_LATCH (1<<7) // special mode to set baud rate36#define LSR 5 // line status register37#define LSR_RX_READY (1<<0) // input is waiting to be read from RHR38#define LSR_TX_IDLE (1<<5) // THR can accept another character to send3940// for sending threads to synchronize with uart "ready" interrupts.41static struct spinlock tx_lock;42static int tx_busy; // is the UART busy sending?43static int tx_chan; // &tx_chan is the "wait channel"4445extern volatile int panicking; // from printf.c46extern volatile int panicked; // from printf.c4748void49uartinit(void)50{51 // disable interrupts.52 WriteReg(IER, 0x00);5354 // special mode to set baud rate.55 WriteReg(LCR, LCR_BAUD_LATCH);5657 // LSB for baud rate of 38.4K.58 WriteReg(0, 0x03);5960 // MSB for baud rate of 38.4K.61 WriteReg(1, 0x00);6263 // leave set-baud mode,64 // and set word length to 8 bits, no parity.65 WriteReg(LCR, LCR_EIGHT_BITS);6667 // reset and enable FIFOs.68 WriteReg(FCR, FCR_FIFO_ENABLE | FCR_FIFO_CLEAR);6970 // enable transmit and receive interrupts.71 WriteReg(IER, IER_TX_ENABLE | IER_RX_ENABLE);7273 initlock(&tx_lock, "uart");74}7576// transmit buf[] to the uart. it blocks if the77// uart is busy, so it cannot be called from78// interrupts, only from write() system calls.79void80uartwrite(char buf[], int n)81{82 acquire(&tx_lock);8384 int i = 0;85 while(i < n){ 86 while(tx_busy != 0){87 // wait for a UART transmit-complete interrupt88 // to set tx_busy to 0.89 sleep(&tx_chan, &tx_lock);90 } 91 92 WriteReg(THR, buf[i]);93 i += 1;94 tx_busy = 1;95 }9697 release(&tx_lock);98}99100101// write a byte to the uart without using102// interrupts, for use by kernel printf() and103// to echo characters. it spins waiting for the uart's104// output register to be empty.105void106uartputc_sync(int c)107{108 if(panicking == 0)109 push_off();110111 if(panicked){112 for(;;)113 ;114 }115116 // wait for UART to set Transmit Holding Empty in LSR.117 while((ReadReg(LSR) & LSR_TX_IDLE) == 0)118 ;119 WriteReg(THR, c);120121 if(panicking == 0)122 pop_off();123}124125// try to read one input character from the UART.126// return -1 if none is waiting.127int128uartgetc(void)129{130 if(ReadReg(LSR) & LSR_RX_READY){131 // input data is ready.132 return ReadReg(RHR);133 } else {134 return -1;135 }136}137138// handle a uart interrupt, raised because input has139// arrived, or the uart is ready for more output, or140// both. called from devintr().141void142uartintr(void)143{144 ReadReg(ISR); // acknowledge the interrupt145146 acquire(&tx_lock);147 if(ReadReg(LSR) & LSR_TX_IDLE){148 // UART finished transmitting; wake up sending thread.149 tx_busy = 0;150 wakeup(&tx_chan);151 }152 release(&tx_lock);153154 // read and process incoming characters, if any.155 while(1){156 int c = uartgetc();157 if(c == -1)158 break;159 consoleintr(c);160 }161}162